Forming integrated inductors and transformers with embedded magnetic cores

ABSTRACT

In accordance with an embodiment of the application a method of forming an integrated magnetic device is described. A prepreg or core is mounted on a carrier. A winding layer is plated and patterned on the prepreg or core. Vias are plated. The silicon is placed on a die attach pad, ensuring sufficient clearance of die to vias and d/a char. The assembly is laminated and grinded to expose the vias. A 2 nd  layer of vias is provided by sputtering or plating followed by laminating assembly; and grinding assembly to expose vias. The windings are plated and patterned. A solder mask (SMSK) is applied and assembly finished.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority under 35 U.S.C. §119(e)of U.S. Provisional Application 61/907,515 filed on Nov. 22, 2013. Saidapplication incorporated herein by reference.

FIELD

This invention relates to the field of integrated circuit packaging and,more specifically, integrated inductors and transformers with embeddedmagnetic cores.

BACKGROUND

Switched power supplies—either as point of load or as DSP cores aremoving to multi phase architectures in order to continuously improveform factor without sacrificing efficiency (from increased switchingloss). This drives the need for high performance coupled inductors thatcan be integrated close to the IC with minimal stray parasitic.

Such integration (arrays of coupled integrated inductors andtransformers) cannot be addressed with discrete inductors. Wafer levelintegration offers a path for performance but at a very high cost,making it non-competitive.

A method is desired to provide Small form factor , high performance andscalable (coupled arrays, transformers, multiphase), low cost.

Many modifications and other embodiments of the invention will come tomind to one skilled in the art to which this invention pertains havingthe benefit of the teachings presented in the foregoing descriptions,and the associated drawings. Therefore, it is to be understood that theinvention is not to be limited to the specific embodiments disclosed.Although specific terms are employed herein, they are used in a genericand descriptive sense only and not for purposes of limitation.

SUMMARY

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summary isnot an extensive overview of the invention, and is neither intended toidentify key or critical elements of the invention, nor to delineate thescope thereof. Rather, the primary purpose of the summary is to presentsome concepts of the invention in a simplified form as a prelude to amore detailed description that is presented later.

In accordance with an embodiment of the application a method of formingan integrated magnetic device is described. A prepreg or core is mountedon a carrier. A winding layer is plated and patterned on the prepreg orcore. Vias are plated. The silicon is placed on a die attach pad,ensuring sufficient clearance of die to vias and d/a char. The assemblyis laminated and grinded to expose the vias. A 2nd layer of vias isprovided by sputtering or plating followed by laminating assembly; andgrinding assembly to expose vias. The windings are plated and patterned.A solder Mask (SMSK) is applied and assembly finished.

In accordance with another embodiment of the present application amethod of forming an integrated magnetic device package is described. Acopper CU sheet is planarized using chemical mechanical planarizing(CMP) or plasma thinning. An insulating layer is applied to the topsurface of the Cu sheet. Magnetic layers are sputtered on the topsurface of the insulating layer. The magnetic layers are patterned andetched. Vias are provided and plated. The vias may include bar vias usedas stiffeners outside of the package body. The magnetic material isannealed in a magnetic field. The assemblies are laminated (prepreg orfilm). The assemblies are grinded to expose vias. The windings areplated and patterned. The top windings are laminated. The CU sheet isstripped from the assembly. The bottom windings are applied andpatterned. A solder mask SMSK is applied and assembly finished.

DESCRIPTION OF THE VIEWS OF THE DRAWING

FIG. 1 is illustrative of package devices with inductors or transformerswith embedded magnetic cores.

FIG. 2 (comprising FIGS. 2A and 2B) is illustrative of a method inaccordance with a first embodiment.

FIG. 3, (comprising FIGS. 3A and 3B), is illustrative of another methodto create a panel based sputtered core in accordance with anotherembodiment.

In the drawings, like reference numerals are sometimes used to designatelike structural elements. It should also be appreciated that thedepictions in the figures are diagrammatic and not to scale.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

The embodiments of the invention are described with reference to theattached figures. The figures are not drawn to scale and they areprovided merely to illustrate the invention. Several aspects of theinvention are described below with reference to example applications forillustration. It should be understood that numerous specific details,relationships, and methods are set forth to provide an understanding ofthe invention. One skilled in the relevant art, however, will readilyrecognize that the invention can be practiced without one or more of thespecific details or with other methods. In other instances, well-knownstructures or operations are not shown in detail to avoid obscuring theinvention. The embodiments of the invention are not limited by theillustrated ordering of acts or events, as some acts may occur indifferent orders and/or concurrently with other acts or events.Furthermore, not all illustrated acts or events are required toimplement a methodology in accordance with the present invention.

Discrete inductors may not suitable for applications with multiphaseswitching where arrays of coupled inductors may be needed

Development with sputtered cores, thick CU windings and SU8 polymers forhigh aspect ratio vias have been investigated. While performance andsize have been demonstrated, the costs of a wafer level integratedinductor are 1.4×-4× more than discretes, making the technologynon-competitive.

Embodiments of the invention aim at leveraging the key performancebenefits from a high performance core (either sputtered or plated) andthe ability of laminate substrates to have thick CU (for low DCresistance).

While there are several approaches to creating inductors with laminates,they are all large and typically have low performance due to eddycurrents and incomplete magnetic paths (typically a race track inductorlayout).

The embodiments describe a solenoid like approach with windings around ahigh performance magnetic core. Typical embedding technologies areconstrained by the thickness of the embedded IC and drilled (mechanicalor laser) via technologies, which require a large via pitch andconsequently a larger inductor with increased resistance. Theembodiments approach use plated vias and panel level grinding to enableembedding cores that are less than 10 um thick, with very dense viapitch (comparable to a wafer level fabrication approach commonly used inapplications with higher current densities that need thick CU and tightinductor coil windings).

Use of a high performance core, planar structure which use CU traces(windings) around a magnetic core allows for a complete magnetic fluxcapture vs racetrack structures or air core structures, wherein ‘tall’via formations using plated vias and panel level grinding enables tight‘windings’, small size and low DRC.

Embedded advanced core with windings on laminate have challenges. Waferswith cores are high stressed and may warp during back grind BG. ThinnestBG may be 50 um using Taiko equipment. Typical embedded applications mayonly handle die at 100 um. Vias that connect top and bottom layerrouting should be taller than the embedded core (magnetic material+Si),and this typically results in coarse windings. Typical drilled vias usedfor embedded applications tend to have 250 um via pitch in HVM and 175um pitch in Proto stage, which do not meet the needs for tight windingsneeded for magnetics. The present embodiments provide an approach toembedding and leveraging built up vias, LDI and panel level chemicalmechanical polishing CMP/plasma thining that allows creation of tightwindings.

FIG. 1 Is illustrative of package devices with inductors or transformerswith embedded magnetic cores. The package 100 includes a substrate 170,attach layer 160, magnetic core 130 on carrier 140. Windings 120surround the magnetic core 130. Vias 150 provide connection path throughfilm 110.

FIG. 2 (comprising FIGS. 2A and 2B) is illustrative of a method inaccordance with a first embodiment:

Step 1 of FIG. 2A, prepreg or core (with appropriate carrier if needed).

Step 2 of FIG. 2A, plating and patterning a winding layer (examplewinding may be 90 um L: 40 um S, 25 um thick). Traces may be etched.

Step 3 of FIG. 2A, plate vias (example: vias may be 65 um tall, <65 umdia, <130 um pitch).

Step 4 of FIG. 2A, place silicon (as example, may be 50-70 um thick) ondie attach pad. Ensure sufficient clearance of die to vias and d/a char.

Step 5 of FIG. 2A, laminate assembly.

Step 6 of FIG. 2A, grind assembly to expose vias.

Step 7 of FIG. 2B, provide 2nd layer of via (can sputter or plate), (anexample: 2nd layer may be 25 um tall, 25 um diameter).

Step 8 of FIG. 2B, laminate assembly.

Step 9 of FIG. 2B, grind assembly to expose vias.

Step 10 of FIG. 2B, plate and pattern windings.

Step 11. of FIG. 2B, solder mask SMSK and finish assembly.

FIG. 3, (comprising FIGS. 3A and 3B), is illustrative of another methodto create a panel based sputtered core in accordance with anotherembodiment.

Step 1 of FIG. 3A, provide and planarize a copper Cu sheet usingchemical mechanical planarizing CMP.

Step 2 of FIG. 3A, apply an insulating layer to the top surface of theCu sheet and then sputter magnetic layers (magnetic layers can be NiFeor Ta2O5) on the top surface insulating layer. Pattern and etch magneticlayers.

Step 3 of FIG. 3A, plate vias (for an example: vias may be 65 um tall,<130 um pitch). Embodiment may include bar vias as stiffeners outside ofthe package body.

Step 4 of FIG. 3A, anneal magnetic material in a magnetic field. Annealchambers may accommodate 16×20 inch panels.

Step 5 of FIG. 3A, laminate (prepreg or film).

Step 6 of FIG. 3A, grind assembly to expose vias.

Step 7 of FIG. 3A, plate and pattern windings.

Step 8 of FIG. 3A, laminate top windings.

Step 9 of FIG. 3A, strip CU sheet from assembly.

Step 10 of FIG. 3A, apply and pattern bottom windings.

Step 11 of FIG. 3A, solder mask SMSK and finish assembly.

The present embodiments provide Small form factor, high performance andscalable (coupled arrays, transformers, multiphase), at low cost.

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only and not limitation. Numerous changes to the disclosedembodiments can be made in accordance with the disclosure herein withoutdeparting from the spirit or scope of the invention. Thus, the breadthand scope of the present invention should not be limited by any of theabove described embodiments. Rather, the scope of the invention shouldbe defined in accordance with the following claims and theirequivalents.

What is claimed is:
 1. A method of forming an integrated magnetic devicepackage assembly, the method comprising: mounting a on a carrier;plating and patterning a winding layer on the core; providing aplurality of vias; plating the plurality of vias; placing silicon on adie attach pad, ensuring sufficient clearance of die to vias; laminatingthe assembly; grinding the assembly to expose the plurality of vias;providing a second layer of vias by sputtering; laminating the assemblyagain; grinding the assembly to expose the vias; plating and patterningthe windings; and solder mask SMSK.
 2. The method of claim 1, whereinthe windings are of 100 um pitch and of 25 um-50 um thickness.
 3. Themethod of claim 1, wherein the silicon is can be 50-70 um thick.
 4. Themethod of claim 1, wherein the second layer of vias is 25 um tall and 25um in diameter.
 5. The method of claim 1, wherein the core is prepreg.6. The method of claim 1, wherein the second layer of vias are plated.7. A method of forming an integrated magnetic device package assembly,the method comprising: planarizing a copper CU sheet; applying aninsulating layer to the top surface of the Cu sheet; sputtering aplurality of magnetic layers on the top surface of the insulating layer;pattern the magnetic layers; etch the magnetic layers; plating aplurality of vias; annealing a magnetic material of the magnetic layersin a magnetic field; laminating the assemblies using film; grinding theassemblies to expose the plurality of vias; plating and patterning aplurality of windings; laminating a top number of windings of theplurality of windings; stripping the CU sheet from assembly; applyingand patterning a bottom number of windings of the plurality of windings;and solder mask (SMSK).
 8. The method of forming an integrated magneticdevice, as recited in claim 7, wherein the magnetic layers are selectedfrom NiFe or Ta2O5.
 9. The method of forming an integrated magneticdevice, as recited in claim 7, wherein anneal chambers can accommodate16×20″ panels.
 10. The method of forming an integrated magnetic device,as recited in claim 7, wherein the vias include bar vias.
 11. The methodof forming an integrated magnetic device, as recited in claim 10,wherein the bar vias are used as stiffeners outside of the package. 12.The method of forming an integrated magnetic device, as recited in claim7, wherein planarizing a copper CU sheet is done using chemicalmechanical planarizing (CMP).
 13. The method of forming an integratedmagnetic device, as recited in claim 7, wherein laminating theassemblies using prepreg instead of film.